Cache的描述(SH2A)
Cache is composed of four ways(banks), each of which is divided into an address section and a data section.
Each of the address and data sections is divided into 128 entries. The data section of the entry is called a line. Each line consists of 16 bytes(4 bytes * 4). The data capacity per way is 2KB(16bytes * 128 entries), with a total of 8KB in the cache as a whole(4 ways).. The instruction cache structure is the same as the operand cache structure except for not having the U bit.
我们可以看到，Cache分为address section和data section两个部分. 它们实际上就是CPU中的一小块RAM，这一小块RAM位于某一地址空间，使用特殊的指令，例如MOV指令，就可以访问这一空间，也就是Cache的内容。例如：
The instruction cache address array is mapped onto address H'F0000000 to H'F07FFFFF, and the data array onto addresses H'F1000000 to H'F17FFFFF. The operand cache address array is mapped onto addresses H'F0800000 to H'F0FFFFFF, and the data array onto addresses H'F1800000 to H'F1FFFFFF.
Cache的有效空间(valid space)
Cache的有效空间是指Cache的工作范围，假设Cache的有效空间为H'00000000 to H'1FFFFFFF，那么在这一范围内的所有数据都可以被Cache访问，如果用户的程序位于有效空间之内，CPU的运算速度就可以大大提高。因此，更改Cache寄存器或者访问Cache内容的代码，要放在Cache有效空间之外，否则程序很容易出错！