智能车制作

标题: CPLD研究 [打印本页]

作者: abcdefg 时间: 2010-4-22 14:15
标题: CPLD研究
module testram3(arm_data,arm_add,arm_oe,arm_we,arm_ce,arm_ctrl,
sram_data,sram_add,sram_oe,sram_we,sram_ce,cpld_rst,sram_state,
cam_data,cam_href,cam_vsyn,cam_pclk,ledout);

input arm_oe,arm_we,arm_ce;
input cam_href,cam_vsyn,cam_pclk;
input [1:0] arm_ctrl; //来自arm的信号，10表示arm读sram，01表示采集图像数据
input cpld_rst; //与arm共用的复位信号，低有效

output sram_oe,sram_we,sram_ce;
output sram_state;

output ledout;

input [18:0] arm_add; //地址总线
output [18:0] sram_add;

inout [7:0] sram_data;//数据总线
output [7:0] arm_data;

input [7:0] cam_data;

reg [18:0] sram_add_map;

reg sram_oe_map,sram_ce_map,sram_we_map;

reg sram_state; //

reg [2:0] current_state;    //状态机状态
reg [2:0] next_state;    //状态机状态

//reg [7:0] arm_data;
//reg [7:0] sram_data_map;

reg vsyn_0,vsyn_1;

//reg [2:0] addback;

reg cur,nex; //时序检测部分状态机
reg temp;    //时序检测的标志位，为1可以开始采集

//reg ledout;
//assign sram_data_map = cam_data;
// assign sram_data = sram_data_map;
assign sram_data = (arm_ctrl == 2'b10) ? 8'hzz : cam_data;
assign arm_data  = (arm_ctrl == 2'b10) ? sram_data : 8'hzz;

assign sram_add  = (arm_ctrl == 2'b10) ? arm_add : sram_add_map;
assign sram_oe = (arm_ctrl == 2'b10) ? arm_oe  : sram_oe_map;
assign sram_ce = (arm_ctrl == 2'b10) ? arm_ce  : sram_ce_map;
assign sram_we = (arm_ctrl == 2'b10) ? arm_we  : sram_we_map;

//assign ledout = 1'b1;
reg ledout;//与上面的语句只能是一个有效
//*************************主程序*****************************
always@(posedge cam_pclk or negedge cpld_rst)
begin
if(!cpld_rst)
begin
sram_add_map <= 19'b0;
vsyn_0 <= 1'b0;

current_state <= 3'b0;//状态机初始化，3位6个状态
cur <= 1'b0;//1位
end
else //复位结束
begin
current_state <= next_state;//状态机状态转换
if(current_state == 0)
cur <= 0;
else
cur <= nex;

vsyn_1 <= cam_vsyn; //临时信号赋值
vsyn_0 <= vsyn_1; //用来检测沿

if((current_state == 2) && (cam_href == 1)) //写信号的上升沿地址加1
begin
sram_add_map <= sram_add_map + 19'b1;
end

if(current_state == 0)
begin
sram_add_map <= 19'b0000000000000000000; //地址复位,无建立时间
end
end
end

//*****************************时序检测部分状态机********************

always@(cur)
begin
case(cur)
0:
begin
if((vsyn_0 == 1) && (vsyn_1 == 0))
begin //帧同步信号的下降沿表示一帧的开始
temp = 1;
nex = 1;
end
else
begin
temp = 0;
nex = 0;
end
end
1:
begin
if((vsyn_0 == 0) && (vsyn_1 == 1))
begin //上升沿表示一帧的结束
temp = 0;
nex = 0;
end
else
begin
temp = 1;
nex = 1;
end
end
endcase
end

//*****************************SRAM读写控制状态机**************************
always@(current_state)
begin
case(current_state)
0:
begin
if(arm_ctrl == 2'b01)
next_state = 1;
else
next_state = 0;
end
1:    //使sram进入写状态
begin
if(temp == 1)
begin
sram_oe_map = 0;
sram_ce_map = 0;
sram_we_map = 1;
next_state = 2;
end
else
next_state = 1;
end
2:    //数据采集阶段
begin
sram_we_map = cam_pclk && cam_href;
if(sram_add_map < 17'b110001100000000000)
next_state = 2;
else
next_state = 3;
end
3: //数据采集结束
begin
if(arm_ctrl == 2'b10)
next_state = 0;
else
next_state = 3;
end

default: next_state = 0;
endcase

end
//**************状态标志输出模块********************
always@(current_state or cpld_rst or arm_ctrl)
begin
if(!cpld_rst)
sram_state = 1'b0;
else
if(current_state == 3)
begin
sram_state = 1'b1;
ledout = 1'b1;
end
else
begin
sram_state = 1'b0;
ledout = 1'b0;
end
end
endmodule

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