这是怎么回事了？
#include <hidef.h> /* common defines and macros */
#include "derivative.h" /* derivative-specific definitions */
#pragma LINK_INFO DERIVATIVE "mc9s12xs128"
void CLKinit(void) //64M
{
CLKSEL=0X00; // clock select register
// 0 0 0 0 0 0 0 0
// aboat clkset_pllset
// 0 System clocks are derived from OSCCLK (fBUS = fOSC / 2).
// 1 System clocks are derived from PLLCLK (fBUS = fPLL / 2).
PLLCTL_PLLON=1; //IPLL Control Register 0 IPLL is turned off. 1 IPLL is on
SYNR =0xc0 | 0x07; // 1100 0111 Synthesizer Register 合成
// 7 8 5 4 3 2 1 0
// VCOFRQ[1:0] SYNDIV[5:0]
//Write: Anytime except if PLLSEL = 1
//Fvco=2*fosc(syndiv+1)/(REFDIV + 1) fosc ji
//fpll=fvco/(2*POSTDIV)
//fBUS=fPLL/2
REFDV=0xc0 | 0x01; // Reference Divider Register
// REFDIV=1
// fvoc=128M
// fpll=128M
// fbus=64M
POSTDIV=0x00; // Post Divider Register
_asm(nop);
_asm(nop);
_asm(nop);
_asm(nop);
while(!(CRGFLG_LOCK==1)); //Flags Register
//0 VCOCLK is not within the desired tolerance of the target frequency.
//1 VCOCLK is within the desired tolerance of the target frequency.
CLKSEL_PLLSEL =1;
}
void PITinit(void)
{
PITCFLMT_PITE=0; //PIT(Periodic Interrupt Timer) Control and Force Load Micro Timer Register
//PIT Module Enable Bit
PITCE_PCE0=1; //PIT Channel Enable Register 1 The corresponding PIT channel is enabled.
void SCI_Transmit(byte data)
{
while(!SCI0SR1_TDRE);//SCI Status Register 1 Transmit Data Register Empty Flag
//Byte transferred to transmit shift register; transmit data register empty
SCI0DRL=data;
}
void SCI_Receive(byte *data)
{
while(!SCI0SR1_RDRF);//SCI Status Register 1 Receive Data Register Full Flag
//Received data available in SCI data register