详情垂询
Low-power timer (LPTMR)
4.6.1 Impacted register
LPTMR_CNR
4.6.2 Features
The LPTMR has been updated to always ensure valid data when reading the LPTMR_CNR value.
4.6.3 Software impact
On each read of the LPTMR counter register, software must first write to the LPTMR counter register with any value. This
will synchronize and register the current value of the LPTMR counter register into a temporary register. The contents of the
temporary register are returned on each read of the LPTMR counter register.
4.6.4 Hardware impact
No hardware changes are required in order to execute existing code from Rev 1.x on Rev 2.x.
Universal asynchronous receiver/transmitters (UART)
4.7.1 Memory map comparison
There are a number of new registers added to the UART0 memory map to support new CEA709.1-B (LON) features. The
new features and control of those features are all implemented as additions to the memory map, so previously existing
registers and bits are unchanged.
The table below shows the memory map differences between revision 1.x devices and revision 2.x devices.
Table 11. Memory map comparison
Location Rev. 1.x devices Rev. 2.x devices
0x4006A021 N/A UART CEA709.1-B Control Register 6
(UART0_C6)
0x4006A022 N/A UART CEA709.1-B Packet Cycle Time
Counter High (UART0_PCTH)
0x4006A023 N/A UART CEA709.1-B Packet Cycle Time
Counter Low (UART0_PCTL)
0x4006A024 N/A UART CEA709.1-B Beta1 Timer
(UART0_B1T)
Table continues on the next page...
发表于 2014-4-27 23:16:53
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