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#include "common.h"
#include "HAL_GPIO.h"
#include "NRF2401.h"
#define WIRE PORTB_BASE_PTR
#define NRF PTB_BASE_PTR
#define MOSI 1
#define MISO 2
#define SCK 3
#define SCE 4
#define CSN 5
#define IRQ 6
unsigned char TX_ADDRESS[TX_ADR_WIDTH]= {0x34,0x43,0x10,0x10,0x01}; //????
unsigned char RX_ADDRESS[RX_ADR_WIDTH]= {0x34,0x43,0x10,0x10,0x01}; //????
char sta;
void Delay(int16 s)
{
unsigned int i;
for(i=0; i<s; i++);
for(i=0; i<s; i++);
}
void inerDelay_us(uint8 n)
{
for(;n>0;n--);
}
uint8 SPI_RW(uint16 unchar)
{
uint16 bit_ctr;
for(bit_ctr=0;bit_ctr<8;bit_ctr++) // output 8-bit
{
if(unchar & 0x80)//output 'uchar', MSB to MOSI
{
LPLD_GPIO_Set_b(NRF,MOSI,1);
}
else
{
LPLD_GPIO_Set_b(NRF,MOSI,0);
}
unchar = (unchar << 1); // shift next bit into MSB..
LPLD_GPIO_Set_b(NRF,SCK,1); // Set SCK high..
unchar |= LPLD_GPIO_Get_b(NRF,MISO); // capture current MISO bit
LPLD_GPIO_Set_b(NRF,SCK,0); // ..then set SCK low again
}
return(unchar); // return read uchar
}
uint8 SPI_Read(uint8 reg)
{
uint8 reg_val;
LPLD_GPIO_Set_b(NRF,CSN,0); // CSN low, initialize SPI communication...
SPI_RW(reg); // Select register to read from..
reg_val = SPI_RW(0); // ..then read registervalue
LPLD_GPIO_Set_b(NRF,CSN,1); // CSN high, terminate SPI communication
return(reg_val); // return register value
}
uint16 SPI_RW_Reg(uint8 reg, uint16 value)
{
uint16 status;
LPLD_GPIO_Set_b(NRF,CSN,0); // CSN low, init SPI transaction
status = SPI_RW(reg); // select register
SPI_RW(value); // ..and write value to it..
LPLD_GPIO_Set_b(NRF,CSN,1); // CSN high again
return(status); // return nRF24L01 status uchar
}
uint16 SPI_Read_Buf(uint8 reg, uint8 *pBuf, uint8 uchars)
{
uint16 status,uchar_ctr;
LPLD_GPIO_Set_b(NRF,CSN,0); // Set CSN low, init SPI tranaction
status = SPI_RW(reg); // Select register to write to and read status uchar
for(uchar_ctr=0;uchar_ctr<uchars;uchar_ctr++)
pBuf[uchar_ctr] = SPI_RW(0); //
LPLD_GPIO_Set_b(NRF,CSN,1);
return(status); // return nRF24L01 status uchar
}
uint16 SPI_Write_Buf(unsigned char reg, unsigned char *pBuf, unsigned char uchars)
{
uint16 status,uchar_ctr;
LPLD_GPIO_Set_b(NRF,CSN,0); //SPI??
status = SPI_RW(reg);
for(uchar_ctr=0; uchar_ctr<uchars; uchar_ctr++) //
SPI_RW(*pBuf++);
LPLD_GPIO_Set_b(NRF,CSN,1); //??SPI
return(status); //
}
void SetRX_Mode(void)
{
LPLD_GPIO_Set_b(NRF,SCE,0);
// SPI_RW_Reg(WRITE_REG + CONFIG, 0x0f); // IRQ????????,16?CRC ,???
LPLD_GPIO_Set_b(NRF,SCE,0);
inerDelay_us(130);
}
uint8 nRF24L01_RxPacket(uint8* rx_buf)
{
uint8 revale=0;
sta=SPI_Read(STATUS); // ????????????????
if(sta&0x40) // ?????????
{
LPLD_GPIO_Set_b(NRF,SCE,0); //SPI??
SPI_Read_Buf(RD_RX_PLOAD,rx_buf,TX_PLOAD_WIDTH);// read receive payload from RX_FIFO buffer
revale =1; //????????
}
SPI_RW_Reg(WRITE_REG+STATUS,sta); //??????RX_DR,TX_DS,MAX_PT????1,???1???????
return revale;
}
void nRF24L01_TxPacket(uint8 * tx_buf)
{
LPLD_GPIO_Set_b(NRF,SCE,0); //StandBy I??
SPI_Write_Buf(WRITE_REG + RX_ADDR_P0, TX_ADDRESS, TX_ADR_WIDTH); // ???????
SPI_Write_Buf(WR_TX_PLOAD, tx_buf, TX_PLOAD_WIDTH); // ????
SPI_RW_Reg(WRITE_REG + CONFIG, 0x0e); // IRQ????????,16?CRC,???
LPLD_GPIO_Set_b(NRF,SCE,1); //??CE,??????
inerDelay_us(10);
}
void init_NRF24L01(void)
{
LPLD_GPIO_Init(WIRE,MISO,0,0,0);
LPLD_GPIO_Init(WIRE,IRQ,0,0,0);
LPLD_GPIO_Init(WIRE,SCE,1,0,0);
LPLD_GPIO_Init(WIRE,SCK,1,0,0);
LPLD_GPIO_Init(WIRE,CSN,1,0,0);
LPLD_GPIO_Init(WIRE,MOSI,1,0,0);
inerDelay_us(100);
LPLD_GPIO_Set_b(NRF,SCE,0); // chip enable
LPLD_GPIO_Set_b(NRF,CSN,1); // Spi disable
LPLD_GPIO_Set_b(NRF,SCK,0); // Spi clock line init high
SPI_Write_Buf(WRITE_REG + TX_ADDR, TX_ADDRESS, TX_ADR_WIDTH); // д±¾µØµØÖ·
SPI_Write_Buf(WRITE_REG + RX_ADDR_P0, RX_ADDRESS, RX_ADR_WIDTH); // д½ÓÊն˵ØÖ·
SPI_RW_Reg(WRITE_REG + EN_AA, 0x01); // ƵµÀ0×Ô¶¯ ACKÓ¦´ðÔÊÐí
SPI_RW_Reg(WRITE_REG + EN_RXADDR, 0x01); // ÔÊÐí½ÓÊÕµØÖ·Ö»ÓÐƵµÀ0£¬Èç¹ûÐèÒª¶àƵµÀ¿ÉÒԲο¼age21
SPI_RW_Reg(WRITE_REG + RF_CH, 0); // ÉèÖÃÐŵÀ¹¤×÷Ϊ2.4GHZ£¬ÊÕ·¢±ØÐëÒ»ÖÂ
SPI_RW_Reg(WRITE_REG + RX_PW_P0, RX_PLOAD_WIDTH); //ÉèÖýÓÊÕÊý¾Ý³¤¶È£¬±¾´ÎÉèÖÃΪ32×Ö½Ú
SPI_RW_Reg(WRITE_REG + RF_SETUP, 0x07); //ÉèÖ÷¢ÉäËÙÂÊΪ1MHZ£¬·¢É书ÂÊΪ×î´óÖµ0dB
SPI_RW_Reg(WRITE_REG + CONFIG, 0x0e); // IRQÊÕ·¢Íê³ÉÖжÏÏìÓ¦£¬16λCRC£¬Ö÷·¢ËÍ
}
没有成功
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