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- 2013-11-6
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- 河北工程大学
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void DMAPer(void)
{
/* int j;
// Clear Destionation memory
for( j=0; j < BUFF_SIZE; j=j+4)
{
*((U32 *)(DESTINATION_ADDRESS+j)) = 0x2E;
}*/
// Enable Clock gating for the DMA and DMA MUX
SIM_SCGC6 |= SIM_SCGC6_DMAMUX_MASK;
SIM_SCGC7 |= SIM_SCGC7_DMA_MASK;
// Config DMA Mux for UART0 operation
// Disable DMA Mux channel first
DMAMUX0_CHCFG0 = 0x00;
// Clear pending errors or the done bit
if (((DMA_DSR_BCR0 & DMA_DSR_BCR_DONE_MASK) == DMA_DSR_BCR_DONE_MASK)
|| ((DMA_DSR_BCR0 & DMA_DSR_BCR_BES_MASK) == DMA_DSR_BCR_BES_MASK)
|| ((DMA_DSR_BCR0 & DMA_DSR_BCR_BED_MASK) == DMA_DSR_BCR_BED_MASK)
|| ((DMA_DSR_BCR0 & DMA_DSR_BCR_CE_MASK) == DMA_DSR_BCR_CE_MASK))
{
DMA_DSR_BCR0 |= DMA_DSR_BCR_DONE_MASK;
}
// Set Source Address (this is the UART0_D register
DMA_SAR0 = SOURCE_ADDRESS;
// Set BCR to know how many bytes to transfer
DMA_DSR_BCR0 = DMA_DSR_BCR_BCR(120); //60
// Clear Source size and Destination size fields.
DMA_DCR0 &= ~(DMA_DCR_SSIZE_MASK
| DMA_DCR_DSIZE_MASK
);
// Set DMA as follows:
// Source size is byte size
// Destination size is byte size
// D_REQ cleared automatically by hardware
// Destination address will be incremented after each transfer
// Cycle Steal mode
// External Requests are enabled
// Asynchronous DMA requests are enabled.
DMA_DCR0 |= (DMA_DCR_SSIZE(1)
| DMA_DCR_DSIZE(1)
| DMA_DCR_D_REQ_MASK
| DMA_DCR_DINC_MASK
| DMA_DCR_CS_MASK //周期挪用位
| DMA_DCR_ERQ_MASK
// | DMA_DCR_EADREQ_MASK //无影响? 异步请求使能位
| DMA_DCR_EINT_MASK //DMA完成中断允许位使能
);
// Set destination address
DMA_DAR0 =(uint32_t)image+CountDone*120; //取image首地址
// Enables the DMA channel and select the DMA Channel Source
DMAMUX0_CHCFG0 = 0x3C; // 总是使能
DMAMUX0_CHCFG0 |= DMAMUX_CHCFG_ENBL_MASK;
DMAMUX0_CHCFG0 |= DMAMUX_CHCFG_TRIG_MASK; //周期触发
// Enable DMA0 IRQ
// pit_init(0,1000); // 1ms
// pit_init(0,1); // 1=1us
pit_ns(0,12); // 1=41ns
enable_irq(DMA0_irq_no);
} |
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