//*================这是我用的PWM配置用于控制电机==================================================
//FTM2 通道0,1PWM输出初始化函数 频率20KHZ PTA10 PTA11
//The edge-aligned mode is selected when (QUADEN = 0), (DECAPEN = 0), (COMBINE
//= 0), (CPWMS = 0), and (MSnB = 1).
//K60P144M100SF2RM.pdf P1011 39.4.6 Edge-Aligned PWM (EPWM) Mode
//The EPWM period is determined by (MOD - CNTIN + 0x0001) and the pulse width
//(duty cycle) is determined by (CnV - CNTIN).
//==========================================================================*/
void FTM2_init(void)
{
// PTA8 K60P144M100SF2.pdf 第68页 8.1 K60 Signal Multiplexing and Pin Assignments
PORTA_PCR10 = PORT_PCR_MUX(0x3)| PORT_PCR_DSE_MASK; // FTM is alt3 function for this pin DSE=1高驱动
PORTA_PCR11 = PORT_PCR_MUX(0x3)| PORT_PCR_DSE_MASK; // FTM is alt3 function for this pin DSE=1高驱动
//FTM1_SC = FTM_SC_PS(0) | FTM_SC_CLKS(1);
//FTM1_SC=0X0F;
FTM2_SC = 0x28; //not enable the interrupt mask,up-down counting mode,System clock,Divide by 0
//FTM1_SC=0X1F; //BIT5 0 FTM counter operates in up counting mode.
//1 FTM counter operates in up-down counting mode.
//BIT43 FTM1_SC|=FTM1_SC_CLKS_MASK;
//00 No clock selected (This in effect disables the FTM counter.)
//01 System clock
//10 Fixed frequency clock
//11 External clock
//BIT210 FTM1_SC|=FTM1_SC_PS_MASK;
//100M MOD=2000;
//000 Divide by 1---12KHZ
//001 Divide by 2--- 6KHZ
//010 Divide by 4--- 3K
//011 Divide by 8--- 1.5K
//100 Divide by 16---750
//101 Divide by 32---375
//110 Divide by 64---187.5HZ
//111 Divide by 128--93.75hz
FTM2_MODE |= FTM_MODE_WPDIS_MASK;
//BIT1 Initialize the Channels Output
//FTMEN is bit 0, need to set to zero so DECAPEN can be set to 0
FTM2_MODE &= ~1;
//BIT0 FTM Enable
//0 Only the TPM-compatible registers (first set of registers) can be used without any restriction. Do not use the FTM-specific registers.
//1 All registers including the FTM-specific registers (second set of registers) are available for use with no restrictions.
FTM2_OUTMASK=0XFC; //0 Channel output is not masked. It continues to operate normally.
//1 Channel output is not masked. It continues to operate normally.
FTM2_COMBINE=0; //Function for Linked Channels (FTMx_COMBINE)
FTM2_OUTINIT=0;
FTM2_EXTTRIG=0; //FTM External Trigger (FTMx_EXTTRIG)
FTM2_POL=0; //Channels Polarity (FTMx_POL)
//0 The channel polarity is active high.
//1 The channel polarity is active low.
//Set Edge Aligned PWM
FTM2_QDCTRL &=~FTM_QDCTRL_QUADEN_MASK;
//QUADEN is Bit 1, Set Quadrature Decoder Mode (QUADEN) Enable to 0, (disabled)
//FTM0_SC = 0x16; //Center Aligned PWM Select = 0, sets FTM Counter to operate in up counting mode,
//it is field 5 of FTMx_SC (status control) - also setting the pre-scale bits here
FTM2_INVCTRL=0; //反转控制
FTM2_SWOCTRL=0; //软件输出控制F TM Software Output Control (FTMx_SWOCTRL)
FTM2_PWMLOAD=0; //FTM PWM Load
//BIT9: 0 Loading updated values is disabled.
//1 Loading updated values is enabled.
FTM2_CNTIN=0; //Counter Initial Value
FTM2_MOD=22500; //Modulo value,The EPWM period is determined by (MOD - CNTIN + 0x0001)
//PMW频率=系统频率/4/(2^FTM1_SC_PS)/FTM1_MOD
//PMW频率=180M/4/(2^0)/2250=150000000/4/2250=20000hz
//PMW分频=180M/4/(2^0)=1406250HZ,一个脉冲是0.7111us,2109个脉冲就是1.5ms
FTM2_C0V=0; //设置 the pulse width(duty cycle) is determined by (CnV - CNTIN).
FTM2_C1V=0; //设置 the pulse width(duty cycle) is determined by (CnV - CNTIN).
FTM2_CNT=0; //只有低16位可用
}