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[其他] 视频分离器LM1881资料[图]

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发表于 2007-7-5 20:34:58 | 只看该作者 回帖奖励 |倒序浏览 |阅读模式
<><IMG src="http://www.intelligentcar.cn/up/l1881.jpg"></P><P>TL H 9150<BR>LM1881VideoSyncSeparator<BR>February 1995<BR>LM1881 Video Sync Separator<BR>General Description<BR>The LM1881 Video sync separator extracts timing informa-<BR>tion including composite and vertical sync burst back porch<BR>timing and odd even field information from standard nega-<BR>tive going sync NTSC PAL and SECAM video signals with<BR>amplitude from 0 5V to 2V p-p The integrated circuit is also<BR>capable of providing sync separation for non-standard fast-<BR>er horizontal rate video signals The vertical output is pro-<BR>duced on the rising edge of the first serration in the vertical<BR>sync period A default vertical output is produced after a<BR>time delay if the rising edge mentioned above does not oc-<BR>cur within the externally set delay period such as might be<BR>the case for a non-standard video signal F<BR>eatures<BR>Y AC coupled composite input signal<BR>Y l10 kX input resistance<BR>Y k10 mA power supply drain current<BR>Y Composite sync and vertical outputs<BR>Y Odd even field output<BR>Y Burst gate back porch output<BR>Y Horizontal scan rates to 150 kHz<BR>Y Edge triggered vertical output<BR>Y Default triggered vertical output for non-standard video<BR>signal (video games-home computers)<BR>Connection Diagram<BR>LM1881N<BR>TL H 9150–1<BR>Order Number LM1881M or LM1881N<BR>See NS Package Number M08A or N08E<BR>PAL in this datasheet refers to European broadcast TV standard ""Phase Alternating Line"" and not to Programmable Array LogicC<BR>1995 National Semiconductor Corporation RRD-B30M115 Printed in U S A<BR>Absolute Maximum Ratings<BR>If Military Aerospace specified devices are requiredp<BR>lease contact the National Semiconductor Sales<BR>Office Distributors for availability and specificationsS<BR>upply Voltage 13 2V<BR>Input Voltage 3 Vpp (VCC e 5V)<BR>6 Vpp (VCC t 8V)<BR>Output Sink Currents Pins 1 3 5 5 mA<BR>Output Sink Current Pin 7 2 mA<BR>Package Dissipation (Note 1) 1100 mW<BR>Operating Temperature Range 0 C b 70 C<BR>Storage Temperature Range b65 C to a150 C<BR>ESD Susceptibility (Note 2) 2 kV<BR>Soldering Information<BR>Dual-In-Line Package (10 sec ) 260 C<BR>Small Outline Package<BR>Vapor Phase (60 sec ) 215 C<BR>Infrared (15 sec ) 220 C<BR>See AN-450 ""Surface Mounting Methods and their Effect on<BR>Product Reliability"" for other methods of soldering surface<BR>mount devicesE<BR>lectrical Characteristics<BR>VCC e 5V Rset e 680 kX TA e 25 C Unless otherwise specified<BR>Parameter Conditions Typ<BR>Tested Design Units<BR>Limit (Note 3) Limit (Note 4) (Limits)<BR>Supply Current Outputs at Logic 1 VCC e 5V 5 2 10 mAmax<BR>VCC e 12V 5 5 12 mAmax<BR>DC Input Voltage Pin 2<BR>1 5<BR>1 3 Vmin<BR>1 8 Vmax<BR>Input Threshold Voltage Note 5<BR>70<BR>55 mVmin<BR>85 mVmax<BR>Input Discharge Current Pin 2 VIN e 2V<BR>11<BR>6 mAmin<BR>16 mAmax<BR>Input Clamp Charge Current Pin 2 VIN e 1V 0 8 0 2 mAmin<BR>RSET Pin Reference Voltage Pin 6 Note 6<BR>1 22<BR>1 10 Vmin<BR>1 35 Vmax<BR>Composite Sync Vertical IOUT e 40 mA VCC e 5V 4 5 4 0 Vmin<BR>Outputs Logic 1 VCC e 12V 11 0 Vmin<BR>IOUT e 1 6 mA VCC e 5V 3 6 2 4 Vmin<BR>Logic 1 VCC e 12V 10 0 Vmin<BR>Burst Gate Odd Even IOUT e 40 mA VCC e 5V 4 5 4 0 Vmin<BR>Outputs Logic 1 VCC e 12V 11 0 Vmin<BR>Composite Sync Output IOUT e b1 6 mA Logic 0 Pin 1 0 2 0 8 Vmax<BR>Vertical Sync Output IOUT e b1 6 mA Logic 0 Pin 3 0 2 0 8 Vmax<BR>Burst Gate Output IOUT e b1 6 mA Logic 0 Pin 5 0 2 0 8 Vmax<BR>Odd Even Output IOUT e b1 6 mA Logic 0 Pin 7 0 2 0 8 Vmax<BR>Vertical Sync Width 230 190 msmin<BR>300 msmax<BR>Burst Gate Width 2 7 kX from Pin 5 to VCC<BR>4<BR>2 5 msmin<BR>4 7 msmax<BR>Vertical Default Time Note 7<BR>65<BR>32 msmin<BR>90 msmax<BR>Note 1 For operation in ambient temperatures above 25 C the device must be derated based on a 150 C maximum junction temperature and a package thermal<BR>resistance of 110 C W junction to ambientN<BR>ote 2 ESD susceptibility test uses the ""human body model 100 pF discharged through a 1 5 kX resistor""N<BR>ote 3 Typicals are at TJ e 25 C and represent the most likely parametric normN<BR>ote 4 Tested Limits are guaranteed to National"s AOQL (Average Outgoing Quality Level)N<BR>ote 5 Relative difference between the input clamp voltage and the minimum input voltage which produces a horizontal output pulseN<BR>ote 6 Careful attention should be made to prevent parasitic capacitance coupling from any output pin (Pins 1 3 5 and 7) to the RSET pin (Pin 6)N<BR>ote 7 Delay time between the start of vertical sync (at input) and the vertical output pulse2<BR>Typical Performance Characteristics<BR>Pulse Separation<BR>vs Vertical Serration<BR>Rset Value Selection<BR>vs Rset<BR>Sync Delay Time<BR>Vertical Default<BR>Gate Time vs Rset<BR>Burst Black Level<BR>Width vs Rset<BR>Vertical Pulse<BR>Width vs Temperature<BR>Vertical Pulse<BR>Supply Voltage<BR>Supply Current vs<BR>TL H 9150–2<BR>3<BR>Application Notes<BR>The LM1881 is designed to strip the synchronization signals<BR>from composite video sources that are in or similar to the<BR>N T S C format Input signals with positive polarity video (in-<BR>creasing signal voltage signifies increasing scene bright-<BR>ness) from 0 5V (p-p) to 2V (p-p) can be accommodatedT<BR>he LM1881 operates from a single supply voltage between<BR>5V DC and 12V DC The only required external components<BR>beside power supply and set current decoupling are the in-<BR>put coupling capacitor and a single resistor that sets internal<BR>current levels allowing the LM1881 to be adjusted for<BR>source signals with line scan frequencies differing from<BR>15 734 kHz Four major sync signals are available from the<BR>I C composite sync including both horizontal and vertical<BR>scan timing information a vertical sync pulse a burst gate<BR>or back porch clamp pulse and an odd even output The<BR>odd even output level identifies which video field of an inter-<BR>laced video source is present at the input The outputs from<BR>the LM1881 can be used to gen-lock video camera VTR<BR>signals with graphics sources provide identification of video<BR>fields for memory storage recover suppressed or contami-<BR>nated sync signals and provide timing references for the<BR>extraction of coded or uncoded data on specific video scan<BR>linesT<BR>o better understand the LM1881 timing information and<BR>the type of signals that are used refer to Figure 2(a–e)<BR>which shows a portion of the composite video signal from<BR>the end of one field through the beginning of the next fieldC<BR>OMPOSITE SYNC OUTPUT<BR>The composite sync output Figure 2(b) is simply a repro-<BR>duction of the signal waveform below the composite video<BR>black level with the video completely removed This is ob-<BR>tained by clamping the video signal sync tips to 1 5V DC at<BR>Pin 2 and using a comparator threshold set just above this<BR>voltage to strip the sync signal which is then buffered out to<BR>Pin 1 The threshold separation from the clamped sync tip is<BR>nominally 70 mV which means that for the minimum input<BR>level of 0 5V (p-p) the clipping level is close to the halfway<BR>point on the sync pulse amplitude (shown by the dashed<BR>line on Figure 2(a) ) This threshold separation is indepen-<BR>dent of the signal amplitude therefore for a 2V (p-p) input<BR>the clipping level occurs at 11% of the sync pulse ampli-<BR>tude The charging current for the input coupling capacitor is<BR>0 8 mA whereas the discharge current is only 11 mA typi-<BR>cally This allows relatively small capacitor values to be<BR>used 0 1 mF is generally recommendedN<BR>ormally the signal source for the LM1881 is assumed to be<BR>clean and relatively noise-free but some sources may have<BR>excessive video peaking causing high frequency video and<BR>chroma components to extend below the black level refer-<BR>ence Some video discs keep the chroma burst pulse pres-<BR>ent throughout the vertical blanking period so that the burst<BR>actually appears on the sync tips for three line periods in-<BR>stead of at black level A clean composite sync signal can<BR>be generated from these sources by filtering the input sig-<BR>nal When the source impedance is low typically 75X a<BR>620X resistor in series with the source and a 510 pF capaci-<BR>tor to ground will form a low pass filter with a corner fre-<BR>quency of 500 kHz This bandwidth is more than sufficient to<BR>pass the sync pulse portion of the waveform however any<BR>subcarrier content in the signal will be attenuated by almost<BR>18 dB effectively taking it below the comparator thresholdF<BR>iltering will also help if the source is contaminated with<BR>thermal noise The output waveforms will become delayed<BR>from between 40 ns to as much as 200 ns due to this filterT<BR>his much delay will not usually be significant but it does<BR>contribute to the sync delay produced by any additional sig-<BR>nal processing Since the original video may also undergo<BR>processing the need for time delay correction will depend<BR>on the total system not just the sync stripperV<BR>ERTICAL SYNC OUTPUT<BR>A vertical sync output is derived by internally integrating the<BR>composite sync waveform (Figure 3) To understand the<BR>generation of the vertical sync pulse refer to the lower left<BR>hand section Figure 3 Note that there are two comparators<BR>in the section One comparator has an internally generated<BR>voltage reference called V1 going to one of its inputs The<BR>other comparator has an internally generated voltage refer-<BR>ance called V2 going to one of its inputs Both comparators<BR>have a common input at their noninverting input coming<BR>from the internal integrator The internal integrator is used<BR>for integrating the composite sync signal This signal comes<BR>from the input side of the composite sync buffer and are<BR>positive going sync pulses The capacitor to the integrator<BR>is internal to the LM1881 The capacitor charge current is<BR>set by the value of the external resistor Rset The output of<BR>the integrator is going to be at a low voltage during the<BR>normal horizontal lines because the integrator has a very<BR>short time to charge the capacitor which is during the hori-<BR>zontal sync period The equalization pulses will keep the<BR>output voltage of the integrator at about the same levelb<BR>elow the V1 During the vertical sync period the narrow<BR>going positive pulses shown in Figure 2 is called the serra-<BR>tion pulse The wide negative portion of the vertical sync<BR></P>

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发表于 2007-8-23 04:06:02 | 只看该作者

Re:视频分离器LM1881资料[图]

能把CCD ,LM1881和单片机的连接电路贴出来啊?
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 楼主| 发表于 2007-8-24 05:21:13 | 只看该作者

Re:视频分离器LM1881资料[图]

<><IMG src="http://www.intelligentcar.cn/up/l1881.jpg"></P><P>其中的摄像头供电电压以你的为准</P><A target=_blank href="http://www.freescalecar.cn/up/l1881.jpg" target=_blank></A>
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 楼主| 发表于 2007-8-24 05:22:19 | 只看该作者

Re:视频分离器LM1881资料[图]

<>也有别的接法 这个只供参考</P>
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发表于 2007-10-5 19:27:03 | 只看该作者

Re:视频分离器LM1881资料[图]

<A target=_blank href="http://www1.demonstudio.cn/ShowPost.asp?ThreadID=35">视频分离器LM1881</A>,懂了。

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发表于 2007-12-11 03:54:37 | 只看该作者

Re:视频分离器LM1881资料[图]

<>资料全是英文的??</P><P>有中文的吗?</P>
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发表于 2009-2-10 23:17:00 | 只看该作者
虽然 是英文  还是谢了
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发表于 2009-11-3 20:41:46 | 只看该作者
有中文的吗
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发表于 2013-3-22 18:23:26 | 只看该作者
为什么是一大屏的代码啊
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