请教帖，K60 ADC+DMA出来的数据不对，求指点

光之子 · 发表于 2012-4-24 17:22:02

ADC输入接地出来的值居然是跳动的。。用的LQ的最小系统
/********************************************************************/
uint8_t ADC_Init(ADC_MemMapPtr adcmap,uint8_t mode, uint8_t diff)
{

  //开启ADC模块时钟
  if (adcmap == ADC0_BASE_PTR)
  {
SIM_SCGC6 |= (SIM_SCGC6_ADC0_MASK);//系统时钟门控制寄存器6,adc0标志位设为1
  }
  else  return 0;

  ADC_Cal(adcmap);
  ADC_SC2_REG(adcmap) &=  ~ADC_SC2_ADTRG_MASK;//软触发

  ADC_SC2_REG(adcmap) |= (ADTRG_SW | ACFE_DISABLED | ACFGT_LESS | ACREN_DISABLED | DMAEN_ENABLED | ADC_SC2_REFSEL(REFSEL_EXT))；
  ADC_SC3_REG(adcmap) &= (~ADC_SC3_AVGE_MASK & ~ADC_SC3_AVGS_MASK);
  ADC_SC3_REG(adcmap) |=  CAL_OFF | ADC_SC3_ADCO_MASK;
  ADC_SC1_REG(adcmap,A) |= (AIEN_OFF | DIFF_SINGLE) ;
  ADC_SC1_REG(adcmap,B) |= (AIEN_OFF | DIFF_SINGLE) ;
  ADC_SC1_REG(adcmap,A) &= ~(ADC_SC1_ADCH_MASK);
  ADC_CFG1_REG(adcmap) |= ADLPC_NORMAL | ADC_CFG1_ADIV(ADIV_1) | ADLSMP_SHORT | ADC_CFG1_ADICLK(ADICLK_BUS) | ADC_CFG1_MODE(MODE_8);

  ADC_CFG2_REG(adcmap) |= MUXSEL_ADCA | ADACKEN_ENABLED | ADHSC_NORMAL;

  return 1;
}

/********************************************************************/
//使能ad函数
uint16_t ADC_SE_Get(ADC_MemMapPtr adcmap, uint8_t channel)
{
if(channel>30)
return 0;

  //不同的通道对应不同的引脚，因此需要判断并配置
  if(adcmap == ADC0_BASE_PTR)
  {
switch(channel)
{
   case 0: //ADC0_DP0 -- PGA0_DP
   case 1: //ADC0_DP1 -- PGA2_DP
   case 2: //PGA0_DP
   case 3: //ADC0_DP3 -- PGA1_DP
      break;
   case 8:  //ADC0_SE8 -- PTB0
   case 9:  //ADC0_SE9 -- PTB1
      SIM_SCGC5 |= SIM_SCGC5_PORTB_MASK;
      PORT_PCR_REG(PORTB_BASE_PTR, channel-8) =  PORT_PCR_MUX(0);
      break;
   case 10:  //ADC0_SE10 -- PTA7
   case 11:  //ADC0_SE11 -- PTA8
      SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
      PORT_PCR_REG(PORTA_BASE_PTR, channel-3) =  PORT_PCR_MUX(0);
      break;
   case 12:  //ADC0_SE12 -- PTB2
   case 13:  //ADC0_SE13 -- PTB3
      SIM_SCGC5 |= SIM_SCGC5_PORTB_MASK;
      PORT_PCR_REG(PORTB_BASE_PTR, channel-10) =  PORT_PCR_MUX(0);
      break;
   case 14:  //ADC0_SE14 -- PTC0
   case 15:  //ADC0_SE15 -- PTC1
      SIM_SCGC5 |= SIM_SCGC5_PORTC_MASK;
      PORT_PCR_REG(PORTC_BASE_PTR, channel-14) =  PORT_PCR_MUX(0);
      break;
   case 16: //ADC0_SE16
      break;
   case 17: //ADC0_SE17 -- PTE24
   case 18: //ADC0_SE17 -- PTE25
      SIM_SCGC5 |= SIM_SCGC5_PORTE_MASK;
      PORT_PCR_REG(PORTE_BASE_PTR, channel+7) =  PORT_PCR_MUX(0);
      break;
   case 19: //ADC0_DM0 -- PGA0_DM
   case 20: //ADC0_DM1 -- PGA2_DM
   case 23: //ADC0_SE23 -- DAC0_OUT
   case 26: //Temperature Sensor (S.E)
   case 27: //Bandgap (S.E)
   case 29: //VREFH (S.E)
   case 30: //VREFL
      break;
   default:
      return 0;
}
  }
  else if(adcmap == ADC1_BASE_PTR)
  {
switch(channel)
{
   case 0: //ADC1_DP0 -- PGA1_DP
   case 1: //ADC1_DP1 -- PGA3_DP
   case 2: //PGA1_DP
   case 3: //ADC1_DP3 -- PGA0_DP
      break;
   case 4: //ADC1_SE4a -- PTE0
   case 5: //ADC1_SE5a -- PTE1
   case 6: //ADC1_SE6a -- PTE2
   case 7: //ADC1_SE7a -- PTE3
      SIM_SCGC5 |= SIM_SCGC5_PORTE_MASK;
      PORT_PCR_REG(PORTE_BASE_PTR, channel-4) =  PORT_PCR_MUX(0);
      break;
   case 8:  //ADC1_SE8 -- PTB0
   case 9:  //ADC1_SE9 -- PTB1
      SIM_SCGC5 |= SIM_SCGC5_PORTB_MASK;
      PORT_PCR_REG(PORTB_BASE_PTR, channel-8) =  PORT_PCR_MUX(0);
      break;
   case 10:  //ADC1_SE10 -- PTB4
   case 11:  //ADC1_SE11 -- PTB5
   case 12:  //ADC1_SE12 -- PTB6
   case 13:  //ADC1_SE13 -- PTB7
      SIM_SCGC5 |= SIM_SCGC5_PORTB_MASK;
      PORT_PCR_REG(PORTB_BASE_PTR, channel-6) =  PORT_PCR_MUX(0);
      break;
   case 14:  //ADC1_SE14 -- PTB10
   case 15:  //ADC1_SE15 -- PTB11
      SIM_SCGC5 |= SIM_SCGC5_PORTB_MASK;
      PORT_PCR_REG(PORTB_BASE_PTR, channel-4) =  PORT_PCR_MUX(0);
      break;
   case 16: //ADC1_SE16
      break;
   case 17:  //ADC1_SE17 -- PTA17
      SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
      PORT_PCR_REG(PORTA_BASE_PTR, channel) =  PORT_PCR_MUX(0);
      break;
   case 18: //VREF Output
   case 19: //ADC1_DM0 -- PGA1_DM
   case 20: //ADC1_DM1 -- PGA3_DM
   case 23: //DAC1_OUT
   case 26: //Temperature Sensor (S.E)
   case 27: //Bandgap (S.E)
   case 29: //VREFH (S.E)
   case 30: //VREFL
      break;
   default:
      return 0;
}
  }
  else
  {
return 0;
  }
  //使能ad通道
  ADC_SC1_REG(adcmap,0) &= ~(ADC_SC1_ADCH_MASK);
  ADC_SC1_REG(adcmap,0) |= ADC_SC1_ADCH(channel);

  return ADC_R_REG(adcmap, 0);
}

DMA使能在行中断里、