CPMUPROT =0x26; //停止保护时钟配置寄存器
CPMUCLKS =0x80; //允许PLL分频
CPMUSYNR =31; //设置分频因子
CPMUPOSTDIV=0x00; // Set the post divider register
CPMUPLL =0x10; // Set the PLL frequency modulation
while(CPMUFLG_LOCK == 0); /* Wait until the PLL is within the desired tolerance of the target frequency */
CPMUPROT=0x00; /* Enable protection of clock configuration registers */
}