void SetBusCLK_nM(byte nM)
{
MMCCTL1=0X00;
PKGCR =0X06;
DIRECT =0x00;
IVBR =0xFF;
ECLKCTL=0xC0;
CPMUPROT =0x26; //停止保护时钟配置寄存器
CPMUCLKS_PSTP=0; //
CPMUCLKS_PLLSEL=1; //应用PLL
//CPMUSYNR =nM-1; //设置分频因子
CPMUSYNR =0xc0|(nM-1); //设置分频因子
CPMUREFDIV =0x80|0x00; //pllclock=2*(1+SYNR)= MHz;
CPMUPOSTDIV=0x00; // Set the post divider register
CPMUPOSTDIV=0x00; // Set the post divider register
CPMUPLL =0x10; // Set the PLL frequency modulation
while(CPMUFLG_LOCK == 0); /* Wait until the PLL is within the desired tolerance of the target frequency */
CPMUPROT=0x00; /* Enable protection of clock configuration registers */
}