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Re:ATD模块中的ATDctl3的作用?
<>If this bit is one (FIFO mode) the conversion counter is not reset at the beginning or ending of a<BR>conversion sequence; sequential conversion results are placed in consecutive result registers. In a<BR>continuously scanning conversion sequence, the result register counter will wrap around when it<BR>reaches the end of the result register file. The conversion counter value (CC2-0 in ATDSTAT0) can<BR>be used to determine where in the result register file, the current conversion result will be placed.<BR>Aborting a conversion or starting a new conversion by write to an ATDCTL register (ATDCTL5-0)<BR>clears the conversion counter even if FIFO=1. So the first result of a new conversion sequence, started<BR>by writing to ATDCTL5, will always be place in the first result register (ATDDDR0). Intended usage<BR>of FIFO mode is continuos conversion (SCAN=1) or triggered conversion (ETRIG=1).<BR>Which result registers hold valid data can be tracked using the conversion complete flags. Fast flag<BR>clear mode may or may not be useful in a particular application to track valid data.<BR>1 = Conversion results are placed in consecutive result registers (wrap around at end).<BR>0 = Conversion results are placed in the corresponding result register up to the selected sequence<BR>length.</P><P>这是说明书上写的,简单说FIFO就是指先进先出存储器,就是将</P><DIV id=result_box dir=ltr>连续转换的值按顺序,写到一个存储区,如果满了的话后面的就会覆盖掉(wrap around at end)</DIV><P>而不是原来的一一对应的地方</P> |
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