根据K10的数据手册和MK10N512MD100头文件分析了复用管脚的用法

阳光少年

Pin Control Register n(PORTx_PCRn)
Bit:  31 30 29 28 27 26 25  24  23 22 21 20  19 18 17 16  15  14 13 12 11  10 9 8  7 6    5   4   3   2   1  0
R:    0  0  0  0  0  0  0   ISF  0  0  0  0  |  IRQC    | LK   0  0  0  0  | MUX|  0 DSE  ODE PFE 0   SRE PE PS
W:                         w1c
Reset:0   0  0  0  0  0  0   0   0   0  0  0  0  0  0  0   0   0  0  0  0   0 0 0  0  0   0   0   0   0   0   0
31-25： Reserved  This read-only field is reserved and always has the value zero.
24： ISF Interrupt Status Flag
   The pin interrupt configuration is valid in all digital pin muxing modes.
   0 Configured interrupt has not been detected.
   1 Configured interrupt has been detected.If pin is configured to generate a DMA request then
     the corresponding flag will be cleared automatically at the completion of the requested DMA
     transfer,otherwise the flag remains set until a logic one is written to the flag.If configured
     for a level sensitive interrupt that remains asserted then flag will set again immediately.
#define PORT_PCR_MUX(x)  (((uint32_t)(((uint32_t)(x))
23-20： Reserved This read-only field is reserved and always has the value zero.
19-16： IRQC Interrupt Configuration
      The pin interrupt configuration is valid in all digital pin muxing modes.The corresponding pin is
      configured to generate interrupt/DMA Request as follows:
      0000 Interrupt/DMA Request disabled.
      0001      DMA Request on rising edge.
      0010      DMA Request on falling edge.
      0011      DMA Request on either edge.
      0100      Reserved
      1000      Interrupt when logic zero.
      1001 Interrupt on rising edge.
      1010 Interrupt on falling enge.
      1011 Interrupt on either edge.
      1100 Interrupt when logic one.
      Others Reserved.
15： LK Lock Register
      0 Pin Control Register bits[15:0]are not locked.
      1 Pin Control Register bits[15:0]are locked and cannot be undated until the next System Reset.
14-11： Reserved This read-only field is reserved and always has the value zero.
10-8 Mux Pin Mux Control
The corresponding pin is configured as follows：

000 Pin Diaabled(Analog).
001 Alternative1(GPIO)
010 Alternative2(chip specific).
011 Alternative3(chip specific).
100 Alternative4(chip specific).
101 Alternative5(chip specific).
110 Alternative6(chip specific).
111 Alternatice7(chip specific).
7： Reserved This read field is reserved and always has the value zero.
6： DSE Drive Strength Enable
      Drive Strength configuration is valid in all digital pin muxing modes.
      0 Low drive strength is configured on the corresponding pin,if pin is configured as a digital output.
      1 Hight dirve strength is configured on the corresponding pin,if pin is configured as a digital output.
5： ODE Open Drain Enabel
Open Drain configured is valid in all digital pin muxing modes.
        0 Open Drain output is disabled on the corresponding pin.
1 Open Drain is enabled on the corresponding pin,provided pin is configured as a digital output.
4： PFE Passive Filter Enable
Passive Filter configuration is valid in all digital pin muxing mode.
0 Passive Input Filter is disabled on the corresponding pin.
1 Passive Input Filter is enabled on the corresponding pin ,provided pin is configured as a digital
   input.A low pass filter(10MHz to 30 MHz baudwidth) is enabled on the digital input path. Disable the
   Passive Input Filter when supporting high speed interfaces(>2MHz) on the pin.
3 ：Reserved This read-only field is reserved and always has value zero.
2 ：SRE Slew Rate Enable
  Slew Rate configuration is valid in all digital pin muxing modes.
  0 Fast slew rate is configured on the corresponing pin,if pin is configured as a digital output.
  1 Slow slew rate is configured on the corresponing pin,if pin is configured as a digital output.
1 ：PE Pull Enable Pull configuration is valid in all digital pin muxing modes.
  0 Internal pull-up or pull-down resister is not enabled on the corresponding pin.
  1 Internal pull-up or pull-down resister is enabled on the corresponding pin,provided pin is configured as a
    digital input.
0 ：PS Pull Select
  Pull configuration is valid in all digital pin muxing modes.
  0 Internal pull-down resister is enabled on the corresponding pin,if the corresponding Port Pull Enable
    Register bit is set.
1 Internal pull-up resister is enable on the corresponding pin,if the corresponding Port Pull Enable Register bit
   is set.


PORTA_PCR0 40049000
PORTA_PCR1 40049004
#define PORTA_PCR0 PORT_PCR_REG(PORTA_BASE_PTR,0)
#define PORTA_PCR1 PORT_PCR_REG(PORTA_BASE_PTR,1)
#define PORT_PCR_REG(base,index) ((base)->PCR[index])
PORTA_BASE_PTR->PCR[0]
PORTA_BASE_PTR->PCR[1]
PORTE_PCR24=PORT_PCR_MUX(0x3)
#define PORT_PCR_MUX(x)                          (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
分析如下：
((uint32_t)(x))
把x强制转换成无符号32位
例如：x=0x3  0011
强制装换后结果为：0000 0000 0000 0000 0000 0000 0000 0011
#define PORT_PCR_MUX_SHIFT 8
把x左移PORT_PCR_MUX_SHIFT位
结果为：0000 0000 0000 0000 0000 0011 0000 0000
((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))
强制转换成无符号32位
结果为：0000 0000 0000 0000 0000 0011 0000 0000
结果在与PORT_PCR_MUX_MASK相与
#define PORT_PCR_MUX_MASK                        0x700u
0000 0000 0000 0000 0000 0011 0000 0000
0000 0000 0000 0000 0000 0111 0000 0000
0000 0000 0000 0000 0000 0011 0000 0000
10  9  8 位为 1 1 0 使能了复用管脚的功能。

201000171238

xiaoboss

0000 0000 0000 0000 0000 0011 0000 0000
0000 0000 0000 0000 0000 0111 0000 0000
0000 0000 0000 0000 0000 0011 0000 0000
10  9  8 位为 1 1 0 使能了复用管脚的功能。
最后不是只有8 9位位1吗？